`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Arizona State University
// Engineers: Brentton Garber, Georgii Tkachuk
// 
// Create Date: 17:28:56 04/01/2013 
// Design Name: switch_latcher_8_bit
// Module Name: switch_latcher_8_bit
// Project Name: Lab 3
// Target Devices: Xilinx Spartan6 XC6LX16-CS324 
// Tool versions: Xilinx ISE 14.2 
// Description: Latches all of the switches from the outside world
//
// Revision: 1
// Revision 0.01 - File Created
//
//////////////////////////////////////////////////////////////////////////////////
module switch_latcher_8_bit(i_switch_bus, reset, sys_clk, o_switch_reg 
    );
input[7:0] i_switch_bus;
input reset, sys_clk;
output reg[7:0] o_switch_reg;

// initialize our result wires
wire[7:0] filtered_switch;

// generate 8 separate switch latcher modules for each switch
genvar i;
generate
	for(i=0; i<8; i=i+1) begin: switches
		switch_latcher_1_bit sl(
			.i_switch(i_switch_bus[i]),
			.reset(reset),
			.sys_clk(sys_clk),
			.o_switch(filtered_switch[i]));
	end
endgenerate

// write the the output every clock cycle
always @(posedge sys_clk)
begin 
	o_switch_reg <= filtered_switch;
end									

endmodule

